Traditional SRAM verification flows can require significant resources to implement and support, and still miss critical errors that result in manufacturing defects. Using the Calibre Pattern Matching automated pattern-based solution provides accurate results, avoids costly mask re-spins, and is easily updated to add newly developed SRAM IP cells.
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Industrial Internet of Things (IIoT) has a market forecast approaching $100 billion by 2020, so it has everyone’s attention right now, except, it seems, Silicon Valley. Turning volumes of factory data into actionable information from the supply chain, to the floor, to operations, and up to management, and potentially to customers, is the key challenge of Industrial IoT deployment. This whitepaper explores IIoT market segments, some examples of the payoff of converting factories to the IIoT, and takes a look forward to what IIoT means in the future.
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High-speed optical networks make it possible for people around the world to instantaneously communicate and share ideas. Tiny MEMS optical switches play a critical role in these enormous optical fiber systems. These switches combine mechanical, optical, and electrical domains, making them a good learning device for MEMS design using Tanner EDA tools. This whitepaper illustrates the creation of a 2x2 optical switch.
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This white paper provides insight into the challenges and need for a robust functional verification infrastructure, plus a means to achieve closure by leveraging Synopsys’ suite of high-end tools and applications. Additionally, best practices followed by Synopsys Professional Services consultants to deliver advanced SoC/ASIC verification solutions to leading customers are explained.
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Conventionally, ASIC design involved development of medium complexity Integrated Circuits (of less than 500,000 gates). These had a cycle time of roughly 6 months, were processed with 0.35u technology, and were essentially made up of core logic and some hard macros, like on-chip SRAMs. With rapid advances in semiconductor processing technologies, the density of gates on the die increased in line with what Moore's law predicted. This helped in the realization of more complicated designs on the same IC. Over the last few years, with the advent of bleeding edge technology applications like HDTV and 3rd generation mobile devices, an increasingly evident need has been that of incorporating the traditional microprocessor, memories and peripherals or in other words the whole system - on a single silicon. This paper attempts to confront various opportunities and challenges, and evolve a strategy that can successfully realize a SoC from concept to silicon. The five key aspects of a successful design strategy discussed here are - Architectural strategy, Validation strategy, DFT Strategy, Synthesis & Backend strategy, and Integration strategy.
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Though we might feel as if we live in a digital-centric world, in the realm of chip design, analog circuitry continues to play a critical role. It is particularly essential with the rise of Internet of Things and mobile applications that interact with the analog “real” world. However, designing with analog intellectual property (IP) to support these high-end designs comes with vastly different challenges when compared to supporting low-end applications. This paper examines five key challenges that design engineers must address to successfully design with analog IP.
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